发明名称 SIMULATING CIRCUIT
摘要 PURPOSE:To realize the high-quality software evaluating device which secures the real time property without complicating the hardware configuration by generating a response in accordance with the analysis result of contents of a transmission buffer and the contents of a memory area and writing it in a reception buffer. CONSTITUTION:A CPU 1 is connected to an analysis part 4 through a serial interface transmission buffer part 2 which holds control data of packages 1 to N from an evaluation object software and a serial interface reception buffer part 3 which holds the response data from the analysis part 4. The analysis part 4 analyzes the control data from the evaluation object software held in the transmission buffer part 2 and uses a memory 5 to perform the processing corresponding to a command number. The analysis part 4 writes the response data as the processing result, namely, each frame of a packet for serial transmission of the reception data format in the reception buffer part 3.
申请公布号 JPH0588930(A) 申请公布日期 1993.04.09
申请号 JP19910273081 申请日期 1991.09.25
申请人 NEC CORP 发明人 KOMAI SHINSAKU
分类号 G06F9/48;G06F9/46;G06F11/22 主分类号 G06F9/48
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