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发明名称
VERIFICATION METHOD FOR LOGIC CIRCUIT DESIGN
摘要
申请公布号
JPH0589197(A)
申请公布日期
1993.04.09
申请号
JP19910252551
申请日期
1991.09.30
申请人
TOSHIBA CORP
发明人
KONO KAZUYOSHI
分类号
G06F11/25;G06F11/26;G06F17/50
主分类号
G06F11/25
代理机构
代理人
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地址
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