发明名称 |
Vertical DMOS transistor with compact geometry - has source terminal connected to source region via self-adjusting contact to gate and source region |
摘要 |
The DMOS transistor in a semiconductor substrate consists of a highly doped Drain area (1) of a first conductivity type, an overlying doped area (2) of the same type, and a doped Zone (3) of a second conductivity type located within the area (2) extending to the semiconductor surface (11). The transistor also includes a Gate electrode (6) insulated from the semiconductor substrate by a Gate oxide layer (7), a silicide Source area (10) and a Source electrode (9). The source electrode substantially covers the source region, which is self adjusting in the process. ADVANTAGE - Increased circuit density, higher reliability, reduced ON-resistance, reduced number of fabrication steps, reduced secondary breakdown.
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申请公布号 |
DE4132526(A1) |
申请公布日期 |
1993.04.08 |
申请号 |
DE19914132526 |
申请日期 |
1991.09.30 |
申请人 |
SIEMENS AG, 8000 MUENCHEN, DE |
发明人 |
WERNER, WOLFGANG, DR., 8000 MUENCHEN, DE |
分类号 |
H01L29/45;H01L29/78 |
主分类号 |
H01L29/45 |
代理机构 |
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