发明名称 |
A LATCH UP FREE, HIGH VOLTAGE, CMOS PROCESS FOR SUB-HALF-MICRON DEVICES |
摘要 |
<p>A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.</p> |
申请公布号 |
EP0396707(B1) |
申请公布日期 |
1993.04.07 |
申请号 |
EP19890912600 |
申请日期 |
1989.10.12 |
申请人 |
HUGHES AIRCRAFT COMPANY |
发明人 |
FARB, JOSEPH, E. |
分类号 |
H01L21/265;H01L21/336;H01L21/8238;H01L27/08;H01L27/092;H01L29/78 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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