发明名称 |
CLOCK CONTROL SYSTEM AND METHOD FOR A PARALLEL VARIABLE SPEED CONSTANT FREQUENCY POWER SYSTEM |
摘要 |
<p>A clock control system for a multiple channel electric power system includes a master clock circuit (28) and control circuitry (40) in each parallel connected channel. The channel control circuits are initially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits (38, 40) are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.</p> |
申请公布号 |
EP0275645(B1) |
申请公布日期 |
1993.04.07 |
申请号 |
EP19870310544 |
申请日期 |
1987.11.30 |
申请人 |
SUNDSTRAND CORPORATION |
发明人 |
BAKER, DONAL EUGENE;BEG, MIRZA AKMAL |
分类号 |
G05F1/00;G04G7/00;H02J3/38;H03L7/00 |
主分类号 |
G05F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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