| 摘要 |
PURPOSE:To reduce the synchronization pull-in time regardless of provision of a wide synchronization pull-in range. CONSTITUTION:A phase error signal (g) of a voltage controlled oscillator 15 generating a carrier is obtained by applying logic control to output data e1, f1 and error signals e3, f3 obtained by applying demodulation and recovering a 16-value orthogonal amplitude modulation wave (a). A logic circuit 7 outputs a negative logic signal point detection signal (k) only when an input signal (a) is at a specific signal point. Furthermore, the voltage controlled oscillator 15 outputs a negative logic carrier synchronization detection signal l. Only the phase error signal (g) at a specific signal point at carrier asynchronization is fed back to the voltage controlled oscillator 15 by applying retiming to the signal (g) at a flip-flop 13 receiving a signal obtained through logic operation of the signals k, l and a recovered clock (h) as clock inputs. An error rate discrimination circuit 18 monitors an error rate in the carrier synchronization process and changes signal points detected by the logic circuit 7 to all signal points when the error rate reaches a prescribed value or below. |
