发明名称 RETRY CONTROL SYSTEM OF DATA TRANSFER
摘要 PURPOSE:To prevent a macro instruction performing a block data transfer of plural words from occupying a long time in a processing time when a bus error generates owing to the abnormality of a bus access time monitoring, regarding the data transfer by a CPU of a micro-program control system. CONSTITUTION:In an interpreter performing a N-word block transfer for 16-bit data, a retry processing is performed by an interruption processing when a bus error generates in the data transfer operation of 16-bit read (SC2) or 16-bit write (SC3). When the retry processing is failed, it is recovered by turning a retry failure flag register on. The interpreter moves to the decoding execution of the macro-instruction of a system control program processing by the immediate interruption of a system task level in a MAP processing when a flag register is turned on and at the same time turns the flag register off.
申请公布号 JPH0581175(A) 申请公布日期 1993.04.02
申请号 JP19910241356 申请日期 1991.09.20
申请人 FUJI FACOM CORP 发明人 WATANABE AKIHITO
分类号 G06F11/00;G06F9/22;G06F11/14;G06F11/30;G06F13/36 主分类号 G06F11/00
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