发明名称 PARALLEL PROCESSOR
摘要 PURPOSE:To efficiently drive plural jobs by reducing the network frozen due to a parity error during the transfer of a message through the network as less as possible. CONSTITUTION:This parallel processor is provided with a judging means 201 for judging information relating to routing in a message which is necessary for determining the route of the message in the network 101, and when a parity error is generated by the information relating to the routing in the message, the message is frozen as a machine check by the means 201. When a parity error is generated by information other than the information concerned in the message, no machine check is executed by the means 201 and the message is transferred to a receiving destination PE 102. The PE 102 executes the parity checks of all messages, and when a parity error is generated, executes machine check interruption.
申请公布号 JPH0581224(A) 申请公布日期 1993.04.02
申请号 JP19910241095 申请日期 1991.09.20
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 NAKAKOSHI JUNJI;HAMANAKA NAOKI;TAKEUCHI SHIGEO
分类号 G06F15/173;G06F15/16 主分类号 G06F15/173
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