发明名称 CLOCK RECOVERY CIRCUIT
摘要 PURPOSE:To recover a stable clock whose phase is not fluctuated with respect to an input burst due to a secular change or a voltage fluctuation with respect to the clock recovery circuit generating the clock signal based on a reception burst signal in an optical subscriber circuit. CONSTITUTION:The circuit is provided with a preamble extract circuit 1 extracting only a preamble signal from a reception burst signal and with a frame extract circuit 3 extracting a frame signal falling at a final bit of a burst. A proportional phase comparator 21 which compares the phase of the preamble signal and the phase of an output of a voltage controlled oscillator 24 to control the voltage controlled oscillator with a control voltage and an integration phase comparator 26 comparing the phase of a frequency division output of the voltage controlled oscillator and the phase of a frame signal and controlling the voltage controlled oscillator with a control voltage of '0' or '1' corresponding to lead/lag of the phase apply proportional integration control to the voltage controlled oscillator 24. Otherwise, a frame signal is inputted to the proportional phase comparator 21 in place of the preamble signal and a PLL by a duplicate loop of proportional integration control is used.
申请公布号 JPH0583240(A) 申请公布日期 1993.04.02
申请号 JP19910239874 申请日期 1991.09.19
申请人 FUJITSU LTD 发明人 SUMIYOSHI HIDEO;NAKAJIMA YOSHIBUMI;FURUYAMA YOSHITO
分类号 H04L7/10 主分类号 H04L7/10
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