| 摘要 |
PURPOSE:To provide an inexpensive multiplication device which can perform the multiplication of bits of higher orders at a high speed. CONSTITUTION:A DSP 1 inputs the higher order bit X1 and the lower order bit X0 of the length measurement data from a memory X and also inputs the higher order bit Y1 and the lower order bit Y0 of the coefficient data from a memory Y respectively. Then the DSP 1 adds 24 bits of higher orders of (X0XY0) to (X1XY0+X0XY1) and latches 24 bits of higher order of this addition through a 1st latch circuit R1. A DSP 2 adds (X1XY1) to 24 bits of higher orders of (X0XY0+X1XY0+X0XY1) latched by the circuit R1. Then the DSP 2 latches the result of addition by a higher order bit R21 and a lower order bit R20 of a 2nd latch circuit R2. |
