发明名称 CLOCK RECOVERY CIRCUIT
摘要 PURPOSE:To recover a clock by using a circuit extracting a preamble signal from a burst signal in an excellent way and an analog phase synchronization oscillator with low power consumption using only the preamble signal to recover an excellent clock signal phase-locked to a reception signal. CONSTITUTION:The circuit consists of a preamble extract circuit 1 extracting only a preamble signal from a reception burst signal and of a phase synchronization oscillator 2 generating a clock signal having a nominal frequency corresponding to the reception burst signal and phase-locked to the extracted preamble signal. Only the extracted preamble signal is inputted to the phase synchronization oscillator to synchronize the phase of an output clock signal with a phase of the reception burst signal to stop the input to the phase synchronization oscillator for a data signal reception period and a burst signal intermittent period thereby self-running the oscillator. The preamble extraction circuit 1 consists mainly of a monostable multivibrator 11 having a pulse width of a preamble period and of a retriggerable monostable multivibrator 12 outputting a signal to inhibit the operation of the monostable multivibrator at the reception of a data signal.
申请公布号 JPH0583241(A) 申请公布日期 1993.04.02
申请号 JP19910239875 申请日期 1991.09.19
申请人 FUJITSU LTD 发明人 NAKAJIMA YOSHIBUMI;FURUYAMA YOSHITO;CHIBA KAZUHARU;SUMIYOSHI HIDEO
分类号 H04L7/10 主分类号 H04L7/10
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