| 摘要 |
PURPOSE:To reduce the chip area of a multiplier of (8X8)-bit table reference formula by reducing the capacity of a ROM cell array and transforming this array into an LSI. CONSTITUTION:A ROM cell array 11 is provided to store the result of multiplication obtained between 4 bits of lower orders of a multiplicand and 4 bits of higher orders of multiplier together with a ROM cell array 12 which stores the result of multiplication obtained between 4 bits of higher orders of the multiplicand and 4 bits of higher orders of the multiplier, a ROM cell array 13 which stores the result of multiplication obtained between 4 bits of lower orders of the multiplicand and 4 bits of lower orders of the multiplier. Then a ROM cell array 14 stores the result of multiplication obtained between 4 bits of higher orders of the multiplicand and 4 bits of lower orders of the multiplier. These results of multiplication outputted from the arrays 11-14 are added together in accordance with the digit parts of the multiplied multiplicand and multiplier. |
