发明名称 ADDRESSING ARITHMETIC CIRCUIT
摘要 PURPOSE:To generate address data on memories constituting plural delay circuits that a physical sound source is equipped with as to the physical sound source and reverberation addition device which simulate the musical sound mechanism of a natural musical instrument. CONSTITUTION:When an external controller 2 outputs a specific instruction, a DSP1 performs arithmetic according to a microprogram. AN ALU7 calculates modification data and mask data MSK for modifying a head address AR and supplies them to an adder 16 and AND circuits 17 and 18 through specific index registers AC8, IX9, and IY10, and a mask register MASK11. The adder 16 adds the modification data to the head address AR to generate a modified head address MAR. Then the AND circuits 17 and 18 mask the head address AR and modified head address MAR with mask data MSK and supply them an actual address TAR to a memory system 20.
申请公布号 JPH0580772(A) 申请公布日期 1993.04.02
申请号 JP19910172833 申请日期 1991.07.12
申请人 YAMAHA CORP 发明人 TAKEUCHI KAZUFUMI
分类号 G10K15/12;G06F12/02;G10H7/02;G10H7/08;H03H17/02 主分类号 G10K15/12
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