UPDATE SYNCHRONIZER

摘要

An update synchronizer includes a two-stage synchronization unit for generating enable signals to select an output signal from among multiple input clock signals of a clock delay multiplexer. The enable signals originate from an asynchronous control signal having a phase different from that of the clock signals. A pre-synchronization logic stage transforms the asynchronous control signal into complementary synchronous control signals for use by the clock synchronization units; these synchronous control signals, in turn, are transformed into complementary selection enable signals having phases within the domains of the input clock signals. This ensures that transitions of the enable signals occur during the same clock period.