| 摘要 |
<p>An ISDN 'S' signal detection and display apparatus including a clock signal generator (20) for synchronizing to the 'S signal' and for developing a frame sync clock, a signal converter (22) for connection across the 'S' interface to develop a 'clean' digital signal corresponding to S-signals received at the 'S' interface, a signal processor (24) responsive to the frame sync clock and operative to sample successive S-signals, a storage buffer (26) for temporarily storing the sampled signals, and a display (28) for reporting and/or displaying the averaged signals (40).</p> |
