发明名称 CONTROL CIRCUIT WITH VALIDITY-DETERMINING ARRANGEMENT
摘要 An arrangement is provided for checking the validity of a sensed-current signal from a current-sensing device. The sensed-current signal represents the current in a line. An associated control circuit utilizes the sensed-current signal to indicate or predict the presence of undesired overcurrent conditions. When such conditions may be present, the sensed-current signal is checked to determine if the sensed-current signal is valid; i.e., whether the sensed-current signal accurately represents the current in the line. If the sensed-current signal is invalid, no trip signal is generated to interrupt the current. If the sensed-current signal is valid, the control circuit generates a trip signal to control operation of a circuit-interrupting device. In a particular arrangement, the load on the current-sensing device is changed to determine if the sensed-current signal is valid. If the sensedcurrent signal is valid, the level of the sensed-current signal remains in a valid range and the overcurrent-detection circuit issues the trip signal. If the sensed-current signal is invalid, the level of the sensed-current signal changes. In response, the control circuit does not issue the trip signal and is reset to an initialized mode to monitor for a valid overcurrent condition in response to the sensed-current signal. In a specific arrangement, the current-sensing device is an iron-core transformer which saturates at high current levels.
申请公布号 CA1315383(C) 申请公布日期 1993.03.30
申请号 CA19880586435 申请日期 1988.12.20
申请人 S&C ELECTRIC COMPANY 发明人 RUTA, JOSEPH W.
分类号 H02H1/04;H02H3/093 主分类号 H02H1/04
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