HIGH SPEED CMOS COMPARATOR WITH HYSTERESIS

摘要

HIGH SPEED CMOS COMPARATOR WITH HYSTERESIS A comparator circuit in accordance with the present invention includes a first stage which is a standard CMOS implementation of a differential amplifier. The differential outputs of the first stage are applied to the inputs of a second differential amplifier stage which is of the same design as the first stage. A hysteresis element is added to the current mirror load of the second stage and is driven by an output of the second stage. This second stage output is applied to a threshold matching single-ended gain stage. The output of the gain stage is applied to a standard CMOS inverter which provides the final comparator output. The hysteresis element is placed internally within the second stage to be driven by the second stage output such that the voltage difference between the differential inputs to the second stage must exceed a preselected threshold voltage before the output to the single-ended gain stage switches state.