| 摘要 |
A process for manufacturing a ferroelectric memory array of stacked-cell design that can be operated in both dynamic and nonvolatile modes. The process deviates from conventional stacked cell array processing at the storage node plate formation stage. A storage node polysilicon layer is conformally deposited, while being in-situ conductively doped, to a depth greater than that necessary to completely fill inter-wordline gaps (if not already planarized) and inter-bitline gaps (in the case of a buried digit line process flow). The storage-node poly layer is then planarized to a level at which poly still covers the entire array. Next, a barrier layer of a refractory metal (e.g., platinum) or of a refractory metal silicide is created on top of the planarized storage-node poly layer. A disposable polyimide layer, which is deposited on top of the barrier layer, is patterned during the same step in which the storage node contact layer and barrier layer are patterned. A silicon dioxide layer is subsequently created via low-temperature chemical vapor deposition. After the this silicon dioxide layer is planarized, thus exposing the polyimide layer remnants, the latter are removed. Next, a PZT dielectric layer is deposited via either the well-known solution-gelatin technique or sputtering. Finally, a refractory metal or refractory metal silicide cell plate layer is deposited. The memory array is completed using standard processing from this point.
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