发明名称
摘要 PURPOSE:To improve the degree of circuit integration of an integrated circuit by generating a pulse signal with less number of wires and elements based on the count value of a counter. CONSTITUTION:When a set signal 18a of a set input terminal 18 is inverted from a logical high to a logical low level, a binary counter 21 counts down a clock signal 17a. When a binary output reaches a prescribed count value NP1 [00001100] at a time t1, an output level of a detecting gate 19 goes to a low potential and a detecting signal 19a is outputted. This signal 19a sets an RSFF22 and the level of a pulse signal output terminal 23 changes from a low to a high level. When a binary output of the counter 21 reaches [00001011] at a time t2, the output of the detection gate 19 is returned to high level and the detection is completed.
申请公布号 JPH0522411(B2) 申请公布日期 1993.03.29
申请号 JP19830003680 申请日期 1983.01.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KUNIHIRA TADASHI;MIZUGUCHI HIROSHI;OOTA YUTAKA;OKADA SHINJI;NAKAMURA MINORU
分类号 H03K23/58;H03K21/08;H03K23/00;H03K23/66 主分类号 H03K23/58
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