| 摘要 |
PURPOSE:To shorten a divide operation time by inputting data to be divided and divisor data, detecting the highest-order bit where '1' appears for the first time, obtaining the difference through the comparison and shifting the division data by the difference of comparison. CONSTITUTION:This divider circuit is provided with detection circuits 13 and 14 to which divisor data and the data to be divided are inputted and detecting the highest order '1' of this divider data and the data to be divided and a comparator 15 comparing the signal detected by the circuits 13 and 14, registers 8 and 9 with a function shifting the difference of the comparison to be outputted from this comparator 15, and a counter 7. Thus, the highest number of loop executions of the division flow becomes 1/(n-bit -1) times compared with the conventional one, and the processing can be performed with the same number as the conventional one even in the lowest number of loop executions, remarkably speeding up the division processing. |
