| 摘要 |
<p>PURPOSE:To provide the synchronizing semiconductor logic integrated circuit having a clock driver operating at a high speed. CONSTITUTION:This circuit includes a master clock driver 1 having an up- counter 1U and a down counter 1D inputting the external clock CLK and outputting two frequency divider clocks CLKA and CLKB, an EXOR gate 4 inputting the two frequency divider clocks CLKU and CLKD with the phase deviated by 90 deg. from the nodal points NU and ND of clock wiring 3U and 3D through local clock drivers 5U and 5D into two input terminals and a plurarity of EXOR gate counters 2G with a D flip-flop 2 inputting the EXOR output signal SO. Thus, operating the clock wiring with the frequency half of the clock CLK frequency to be inputted from the external part, simplifying the layout design of the circuit operating at 110MHz.</p> |
