| 摘要 |
A system for backing up volatile memory such as DRAM with non-volatile memory such as EEPROM includes a volatile memory having refresh logic for cycling through the volatile memory address locations and refreshing the contents thereof, and a non-volatile memory having write logic for writing data into an address location of the non-volatile memory over a write cycle. Each of the volatile and non-volatile memories has its own address bus, and the address buses are connected together for reading out the contents of corresponding address locations of the two memories in the same sequence according to the cycle dictated by the volatile memory refresh logic. The contents read out of each corresponding pair of address locations of the volatile and non-volatile memories are compared in the sequence, and if a difference is detected between the compared contents the address buses are disconnected and a write cycle of the non-volatile memory is initiated to transfer data representing the contents of the address location of the volatile memory found to differ into the corresponding address location of the non-volatile memory.
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