| 摘要 |
A scan path composed of a plurality of scan registers comprises a first test mode for testing a RAM, a second test mode for testing a logic circuit and a normal mode. In the first test mode, expected value data is set in each of latch circuits of the scan register. The expected value data held by the latch circuits are determined whether their logics coincide with data read from the RAM in a determination circuit. As a result of this determination, when a fault is occurring in the RAM, the logic of the data held by the latch circuit is inverted. In the second test mode, test data is set in each of latch circuits of the scan register, and the test data set are supplied to the logic circuit. In the normal mode, data read from the RAM is supplied to the logic circuit through the selector circuit without passing through the shift register. Accordingly, the delay time of data propagation path in the normal mode is extremely small and it does not degrade the speed performance of the semiconductor integrated circuit devices. |
