| 摘要 |
A BICMOS bit line load for a memory includes first and second bipolar transistors having emitters respectively coupled to first and second bit lines of a differential bit line pair. Collectors of the first and second bipolar transistors receive a reference voltage. An equalization signal is applied to bases of the first and second bipolar transistors. The equalization signal is at a logic low voltage during a write cycle, and at a logic high voltage otherwise. In order to decrease the worst-case reverse bias, which causes bipolar transistors to degrade over time, a difference between the logic high voltage and the logic low voltage of the equalization signal is limited to a predetermined voltage.
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