CLOCK GENERATOR FOR NETWORK SYNCHRONIZATION

摘要

The circuit processes the data transmitted between networks without loss by supplying clock locked to both the clock of an oscillator and the reference clock. It includes a processor interfacing circuit (1) for processing oscillation control signal and data from a processor, a control signal generator (2) for generating buffer enable signal and latch enable signal, a latch circuit (4), a OVCXO (7) for controlling the frequency of the output clock, and a buffer circuit (3) for buffering the oscillator control signal and data.