| 摘要 |
PURPOSE:To keep phase synchronization even when a bit timing location is not clear by leading a Q component of a reception signal to a phase comparator circuit without any modification for a carrier preamble period and leading its mean value to the phase comparator circuit for a clock preamble period. CONSTITUTION:A bit timing extract circuit 3 extracts a bit timing from an output of an orthogonal detection circuit 11 and a changeover control circuit 16 outputs a switching signal depending whether a period is a carrier preamble period or a clock preamble period. Then a switch 14 is thrown to the position of a terminal (a) for a carrier preamble period and a Q component of a reception signal is led to a phase comparator circuit 15 without any modification, in which phase synchronization is implemented based on a phase error of I,Q components. Then the switch 14 is thrown to the position of terminal b) for a clock preamble period and a mean value of the Q component obtained by an integration device 13 is led to the phase comparator circuit 15. Since the mean value of the Q component is zero, the leadout output is unchanged from that for the carrier preamble period and phase synchronization is implemented similarly. |
