| 摘要 |
A second-order digital sigma-delta modulator uses a single multibit parallel adder (AD) in time division multiplex fashion with an integration delay circuit (DL3) between the output of the adder and the output quantizer (TD), the output of the integration delay circuit being also coupled to one adder input through a 2-way multiplexer switch (SW1) and to the other adder input via an additional delay circuit (DL4). In one position of the switch, an input sample is added to the output of the additional delay circuit and in the other, outputs from both delay circuits are added. To account for the absence of subtractors fed from the quantizer, some of the bits outputted by the integration delay circuit are passed in inverted form, both to the additional delay circuit (INV3) and, from the inverted (INV1) output of the quantizer eventually through a third delay circuit (DL5), to the switch. <IMAGE>
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