发明名称 METHOD FOR FLATTENING RESIST
摘要 PURPOSE:To obtain excellent flatness and to prevent a processing atmosphere from being polluted by the generated gases from a resist prepd. by dissolving specific cresol novolak into ethyl cellosolve acetate in a high-temp. processing stage after formation of the resist by applying the above-mentioned resist on a substrate and processing the substrate by two stages of baking. CONSTITUTION:The semiconductor substrate 2 having ruggedness is prepd. and the resist 3 prepd. by dissolving the o-cresol novolak having 700 to 17000 mol.wt. into the ethyl cellosolve acetate is applied on this substrate 2. The substrate 2 coated with the resist 3 is then baked at 180 to 220 deg.C. Further, the resist 3 subjected to the 1st baking stage is baked at 270 to 300 deg.C. The 1st baking to be executed at 180 to 220 deg.C in such a manner acts to flatten the applied resist 3 and the 2nd baking to be executed at 270 to 300 deg.C exists in the resist and acts the expel the gases generated by thermal decomposition, etc., in a heating stage.
申请公布号 JPH0561206(A) 申请公布日期 1993.03.12
申请号 JP19910219705 申请日期 1991.08.30
申请人 OKI ELECTRIC IND CO LTD 发明人 UESUGI TAKESHI
分类号 G03F7/38;H01L21/027 主分类号 G03F7/38
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