| 摘要 |
PURPOSE:To suppress a limit cycle by providing a 2nd multiplier means multiplying a coefficient whose output is 0 or -1 depending whether an output of a delay means is positive or negative and a subtractor means for outputs 1st and 2nd multiplier means to the filter without discriminating the polarity of the result of the multiplication. CONSTITUTION:A digital signal X from an input terminal 1 is inputted to a delay circuit 2 via an adder 4, in which the signal is delayed by a prescribed time and an output signal Y is outputted from an output terminal 5. Moreover, an output signal XM of the circuit 2 is multiplied with a multiplier coefficient (b) at a multiplier 3 and multiplied with a multiplier coefficient be at a multiplier 6 respectively. Then an output YM of the multiplier 3 is subtracted by an output of the multiplier 6 at a subtractor 7 and the resulting signal YM' is added to the digital input signal X at an adder 4. Then the result is inputted again to the circuit 2. A prescribed characteristic is given to the signal X by applying the processing to the signal repetitively to output the signal Y from the terminal 5. Thus, the limit cycle is suppressed without discriminating the polarity of the result of multiplication. |
