Signal processor with I/O for digital telephone communication - has number of serial and parallel data interfaces in I/O unit together with clock generator coupled to control stages

摘要

The signal processor has a ROM/RAM memory with an address unit, a processor, control unit, programme memory and an I/O unit. The I/O unit has two serial interfaces (28, 29) for data input, two interfaces (30, 31) for data output and parallel interfaces (32, 33) for input and output. Each interface connects with the data base (34) and each has a switching stage generating a set signal (S1 - S6). A clock generator (35) provides inputs (NT, AT) to the interfaces and is coupled to an instruction decoder (36). The generator is activated by the output of a switching stage (38). A register (39) holds control values (E1 - E7) fed to the switching stage. Enable signals are generated by a separate unit (41). ADVANTAGE - Provides I/O flexibility.