| 摘要 |
PURPOSE:To reduce an effect due to variations of a process by keeping the pull-down effect of a bit line unchanged by constructing a transistor by connecting in series memory transistors. CONSTITUTION:n Channel bypassing transistors 31 to 34 are constructed in the same structure as that of a memory transistor using a minimum design rule, and those transistors are disposed in series to ensure a predetermined transistor size. This structure is accordingly such that the c channel current bypassing transistors 31-34 and the transistor using a minimum design rule, are changed, interlocked upon the variations of a process. Thus, since performance of the transistor for supplying a potential to bit lines BL1-BL4 is varied as in the n channel current bypassing transistors 31-34, the pull-down effect of the bit lines is kept unchanged. Thus, stable operation is ensured without being affected by process variations. |
