| 摘要 |
PURPOSE:To obtain a digital phase locked loop circuit activated at a high speed with simple circuit configuration in which phase adjustment of a recovered clock signal is easy. CONSTITUTION:A phase comparator 11 compares the phase of a data signal with the phase of a recovered clock signal and outputs a phase error signal. A phase error storage counter 12 receives a phase error signal and outputs a frequency division offset selection signal. A frequency division offset circuit 13 decides a frequency division offset based on a frequency division offset selection signal. A frequency division counter 14 loads the frequency division offset as an initial value, frequency-divides a master clock and outputs a recovered clock signal to obtain a high speed recovered clock signal with simple circuit configuration. |
