发明名称 POWER CONTROLLER FOR COMPUTER
摘要 <p>PURPOSE:To prevent the complexity of the control and to realize the low-power consumption of the device by operating the system by the proper clock according to the operational state of the system. CONSTITUTION:A clock selection circuit 15 switches a selector 19 to a 1MHz oscillator 21 when a processor state signal (p) is in an idle state, an interrupt signal (i) is inputted, and a signal is inputted from a system bus monitoring circuit 17. Then, a clock control part 11 supplies a 1MHz-clock frequency system clock (s) to a processor 1, a main memory 5, and an I/O control part 7. In this case, when the processor 1 executes the process, the clock selection circuit 15 switches the selector 19 to a 10MHz oscillator 23 when an interruption is generated in the I/O control part 7 or when a system bus 3 is used for data transfer. Then the clock control part 11 supplies the 1MHz-clock frequency system clock (s) to the processor 1, main memory 5, and I/O control part 7.</p>
申请公布号 JPH0553680(A) 申请公布日期 1993.03.05
申请号 JP19910211690 申请日期 1991.08.23
申请人 TOSHIBA CORP 发明人 SANO YOSHINOBU
分类号 G06F1/32;G06F1/04 主分类号 G06F1/32
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