| 摘要 |
PURPOSE:To provide a load circuit for bit lines, which has an excellent applicability relative to its operation, by providing transistors so that the directions of their channels are made respectively vertical to the direction, in which an angle offset is formed when implanting ions. CONSTITUTION:By implanting ions, impurities are formed, and bit lines including at least a pair of transistors T1, T2 are provided, and further, the potentials of bit lines BL, BLD with which a plurality of memory cells are in connection, are set identical with predetermined potentials respectively. At least a pair of transistors T1, T2 is so provided that the directions of their channels are made respectively vertical to the direction, in which an angle of 1 deg. or layer is formed between the axis vertical to the surface of a substrate and the direction ID of implanting ions. Thereby, at the source terminals or drain terminals of the respective transistors, no parasitic resistance, is generated due to offset regions. Therefore, the load circuit for the bit lines, which has a high applicability and wherein the amplitudes when operating the bit line are not different from each other according to logical states, can be realized. |
