| 摘要 |
<p>A semiconductor memory device includes address transition detection means for detecting a change of an address signal and generating a transition pulse signal representing a transition state of the address signal, control means for generating first and second control signals for reading data from a memory cell in response to the transition signal, read means turned ON in response to the first control signal, for reading out the data from the memory cell, output means for latching and outputting output data of the read means in accordance with the second control signal, and reset release means for generating a reset release signal by detecting the change of the second control signal and supplying it to the control means. When the control means is reset by noise and generates the second control signal having a width below a predetermined width, the reset release means detects the change of this second control signal and supplies the reset release signal to the control means. Receiving the reset release signal, the control means releases the reset state of its own and generates the second control signal having a predetermined pulse width.</p> |
