| 摘要 |
<p>A processor (22) for a multiprocessor system comprises a plurality of memories (30,31,32) each for storing a data set. A data path (24) communicates data to the memories (30,31,32). A controller (33) alternately enables and disables transfer of renewal data for updating the data set from the data path (24) to different ones of the memories (30,31,32). An executive unit (29) reads at least a portion of the data set stored in a disabled one of the memories (30,31,32). Renewal means (34) communicates at least a portion of the data set stored in an enabled one of the memories (30,31,32) to the disabled one of the memories (30,31,32) in response to that disabled one of the memories (30,31,32) being re-enabled by the controller (33). <IMAGE></p> |
