CPU expansive gradation of I/O interruption subclass recognition.
摘要
A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions. <IMAGE>
申请公布号
EP0529384(A1)
申请公布日期
1993.03.03
申请号
EP19920113577
申请日期
1992.08.10
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
CHOU, NORMAN CHO-CHUN;GUM, PETER HERMON;HOUGH, ROGER ELDRED;KIM, MOON JU;MAZUROWSKI, JAMES CHESTER;MCCAULEY, DONALD WILLIAM;SCALZI, CASPER ANTHONY;SCANLON, JOHN FENTON;WYMAN, LESLIE WOOD