DELAYED CACHE WRITE ENABLE CIRCUIT FOR A DUAL BUS MICROCOMPUTER SYSTEM WITH AN 80386 AND 82385

摘要

BC388-G06 DELAYED CACHE WRITE ENABLE CIRCUIT FOR A DUAL BUS MICROCOMPUTER SYSTEM WITH AN 80386 AND 82385 In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cacne memory components and at the same time does not impact wait state parameters for read miss operations.