发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To detect superframe marker quickly to shorten the detecting time for superframe by providing the detecting sequence between synchronizing word and reverse synchronizing word as detecting condition for all combinations. CONSTITUTION:From a received data string RD, synchronous word SW and reverse synchronous word ISW are detected by the first detecting means 2. This detected SW and ISW are counted by counter 6 that acts in the frame synchronizing mode, thereby holding 3 consecutive frames in a holding means 4. Next, a sequence of detecting SW and ISW of 3 consecutive frames that are output successively from the holding are provided as detecting condition for all combinations and is detected by the second detecting means 8. With this, at the time when 3 frames including superframe marker are received, the superframe marker is detected.
申请公布号 JPH0548594(A) 申请公布日期 1993.02.26
申请号 JP19910208261 申请日期 1991.08.20
申请人 FUJITSU LTD 发明人 ISHII YOSHINORI
分类号 H04J3/06;H04L7/08;H04L25/49 主分类号 H04J3/06
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