发明名称 BUS MONITORING TIMER CONTROL SYSTEM
摘要 PURPOSE:To simplify the control and to reduce the hardware amount by one system of start/enable control for a timer monitoring operation in the bus monitoring timer control system monitoring the abnormality generation of a bus while timer-monitoring busses. CONSTITUTION:The bus monitoring timer control system is provided with a processor control means 12 supporting the access from a processor 11 and outputting a signal suppressing a clock signal to be outputted by the processor 11, a timer monitoring means 13 executing the monitoring of the bus for constant time and outputting a time-out signal in the lapse of the monitoring time, a time-out status generation part 14 inputting a time-out signal to hold a time- out state and outputting a time-out status signal. At the access request for busses 5 and 7, the processor control means 12 outputs a clock inhibit signal as needed and executes the access while extending the access time. It starts the timer monitoring means 13 by a clock inhibit signal so as to monitor an inhibit state for constant time.
申请公布号 JPH0546497(A) 申请公布日期 1993.02.26
申请号 JP19910201640 申请日期 1991.08.12
申请人 FUJITSU LTD 发明人 YAMAGUCHI TATSUYA;SUDO KIYOSHI;OGURA KIMINARI;SAKURAI YASUTOMO;ODAWARA KOICHI;NONAKA TAKUMI;KANETANI EIJI
分类号 G06F11/00;G06F11/30;G06F13/00 主分类号 G06F11/00
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