发明名称
摘要 PURPOSE:To prevent the lowering of the gate withstand voltage and the like of the titled transistor by a method wherein SOS/MOSFET is isolated by the polycrystalline silicon oxide film containing high density impurities. CONSTITUTION:A high density polycrystalline silicon is selectively formed on a sapphire substrate 1, a silicon single-crystal substrate 2 and a polycrystalline silicon are formed by performing CVD, and the above is wet-oxidated at the temperature of approximately 950 deg.C for about 40min, about 0.1mum of the oxide film on the substrate 2 is removed, the surface of which is made into line with the oxide film 13 which was formed by oxidating the polycrystalline silicon, the oxide film of approxiamtely 400Angstrom to be used for gate is formed, an oxide film 3 for gate of about 400Angstrom is formed, an oxide film 4 for isolation and a CVD oxide film 6 are formed, and then a wiring 7 is provided.
申请公布号 JPH0514430(B2) 申请公布日期 1993.02.25
申请号 JP19810081416 申请日期 1981.05.28
申请人 NIPPON ELECTRIC CO 发明人 FUKUMA MASAO
分类号 H01L21/762;H01L27/12;H01L29/78;H01L29/786 主分类号 H01L21/762
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