发明名称 |
CIRCUIT FOR SAMPLING COMPONENT SIGNALS AND REGENERATING CIRCUIT |
摘要 |
<p>A circuit for sampling component signals and a regenerating circuit comprising a DELTA t delaying circuit (5) which delays the phase of a first analog component signal (I1) by a time DELTA t = (n-1)/(2fs), a first A/D converter (1) which samples the output of the DELTA t delaying circuit (5) with clocks of a sampling frequency fs and generates a first digital data (O1), a 1/n frequency dividing circuit (4) which divides the clock of the sampling frequency fs and generates a clock of a frequency of fs/n (n is a positive integer other than 1), and a second A/D converter (2) which samples a second analog component signal (I2) being in-phase with the first analog component signals (I1) with the clock of fs/n outputted from the 1/n frequency dividing circuit (4) and generates second digital data (O2). <IMAGE></p> |
申请公布号 |
EP0496000(A4) |
申请公布日期 |
1993.02.24 |
申请号 |
EP19910914223 |
申请日期 |
1991.08.09 |
申请人 |
FUJITSU LIMITED |
发明人 |
OKAZAKI, TAKESHI, JUNES SHUWA 202 |
分类号 |
H04N11/08;H04N7/24;H04N9/64;H04N11/04;H04N11/10;H04N11/24;(IPC1-7):H04N11/04 |
主分类号 |
H04N11/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|