| 摘要 |
The switching node is provided with at least one switching element, which has a number n of input lines (E1,...,En) and a number n of output lines (A1,...,An) which can be connected as required via a space switch (RK) to the input lines. A buffer memory (PS1,...,PSn) is allocated to each of the input lines, in which k data packets can be stored and which has m </= k outputs, via which m data packets can be fed simultaneously to the space switch which has mxn inputs and n outputs. The memory addresses under which the data packets to be forwarded are stored in the individual memories are stored, according to the address signals contained in the data packets, in queuing memories (AP1,...,APn) allocated to the output lines. The queuing memories can be activated cyclically from a central control unit (ZST) in order to prepare memory addresses. By means of memory addresses prepared in this way, the central control unit controls both the setting of the space switch (RK) and the output of data packets from the buffer memories (PS1,...,PSn).
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