| 摘要 |
<p>A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator (20), a divider (14), a phase comparator (15), and an up-down counter (16). The ring oscillator (20) provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider (14) divides the oscillation frequency from the ring oscillator (20) by a specified number. The phase comparator (15) compares the frequency of the signal from the divider (14) with the frequency of the external clock signal (Sfe). The up-down counter (16) controls the oscillation frequency of the ring oscillator (20) based on the comparison result from the comparator (15). The clock generator is controlled by an external clock signal (Sfe) to generate an Internal clock signal (Sfc) having a higher frequency and outputs both signals. By use of a digital integrated circuit technology alone, it becomes possible to include slow operating semiconductor elments and fast operating semiconductor elements on the same circuit chip without sacrificing the excellent characteristics of the latter. <IMAGE></p> |
