发明名称 DIGITAL PLL CIRCUIT
摘要 PURPOSE:To increase the frequency pull-in range without generating the folded element of a phase error signal and with no limit cycle due to the folded element. CONSTITUTION:A complex multiplier 13, whose one complex signal is an input and the other one is a carrier input with cosine or cosine characteristic, performs the complex multiplication. The phase error of the output is detected by the sinewave phase comparison characteristic by a phase error detection part 15 and a phase error conversion part 16. The phase error output is smoothed by a loop filter 17, to be inputted to the oscillation frequency control of a numerical control oscillator 18. The output of the numerical oscillator 18 is converted into the sine or cosine characteristic in a data converter 19 to be outputted as a carrier.
申请公布号 JPH0541662(A) 申请公布日期 1993.02.19
申请号 JP19910197788 申请日期 1991.08.07
申请人 TOSHIBA CORP;TOSHIBA AVE CORP 发明人 TAGA NOBORU;ISHIKAWA TATSUYA;KOMATSU SUSUMU
分类号 H03L7/085;H03L7/087;H04L27/00;H04L27/233 主分类号 H03L7/085
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