发明名称 CLOCK SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To provide a clock signal generating circuit in which a dot clock used to control a system with a simple digital circuit without employing a complicated analog circuit technology and making the system expensive in the system superimposing a picture generated from the graphic system onto a video signal. CONSTITUTION:The circuit generating a clock signal 7 by frequency-dividing a reference clock signal 4 starts the generation of the clock signal 7 by using an external control signal 11 as a trigger and is provided with another frequency divider circuit 3 starting the generation of the clock signal 7 by using an external control signal 11 and frequency-dividing the generated clock signal 7, and when the frequency divider circuit 3 generates the clocks by a prescribed clock number, the application of the reference clock 4 to the clock frequency divider circuit 2 is controlled to stop the clock output.
申请公布号 JPH0541813(A) 申请公布日期 1993.02.19
申请号 JP19910196727 申请日期 1991.08.06
申请人 SEIKO EPSON CORP 发明人 NAKAMURA ATSUSHI
分类号 H03L7/00;H04N5/06 主分类号 H03L7/00
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