发明名称 FAULT DETECTOR FOR CACHE MEMORY
摘要 PURPOSE:To detect a fault without separating an ordinary cache operation by writing fault test information on the position of address managing tag information when no address information that matches with a tag memory circuit exists. CONSTITUTION:When unmatching between the address managing tag information 28 and output information from a selection circuit 13 is obtained, the position of the address managing tag information selected by index information 17 is selected as a rewrite target, and is rewritten in plural number of times of bus cycles. In parallel with the above operation, a control means 15 outputs a signal 23 to suppress the output of a response signal 26 to a CPU 1 and a selection signal 21 from access tag information 18 to the fault test information 19 to an output circuit 16. The signal is written on the position of the address managing tag information that becomes the rewrite target by the output information of the selection circuit 13 on the fault test information 19 side. After that, a control signal 32 is outputted from the control means 15, and an address managing tag information 28 is read out from a tag memory circuit 9.
申请公布号 JPH0540691(A) 申请公布日期 1993.02.19
申请号 JP19910193378 申请日期 1991.08.02
申请人 NEC CORP 发明人 TAKEUCHI HIDEYO
分类号 G06F11/22;G06F12/08 主分类号 G06F11/22
代理机构 代理人
主权项
地址