| 摘要 |
<p>The arrangement described has storage cells consisting of MOS transistors and trench capacitors in which the trench (7) is automatically adjusted to primary word lines (4) and insulation regions (2). Both capacitor electrodes are arranged inside the trench and the first electrode is connected to the selector transistor via a contact on the trench wall. A bit line (20, 21) running partly over and partly in the trench and insulated from the second electrode by a third and fourth insulating layer (17, 18) has a contact at this point with the conducting region of the adjacent selector transistor. The storage matrix is made up of rows of storage cells running in the direction of the bit line, whereby the storage cells in the same row have the selector transistor on one side of the capacitor and the next row has it on the other. Particularly reliable evaluation is achieved by two-layer metallisation with a special arrangement of primary, secondary and tertiary word lines (4', 40, 41).</p> |
