发明名称 |
Logic signal level conversion circuit - uses reference stage to ensure defined level adjustment independent of temp. variations |
摘要 |
The logic signal level conversion circuit allows binary signals from a logic level having one switch threshold (P1) to be supplied to a second logic level with a different switch threshold (P2), under control of the input signal for the first logic level. The signal conversion stage (U) has a variable transmission characteristic. A reference stage (R), with the same structure and exhibiting the same transmission characteristic, receives the first switch threshold (P1) at its input (ER). The output of the threshold stage (R) is compared with the second switch threshold (P2) via a comparator (K) to provide a control signal for the transmission characteristics of both the reference stage (R) and the signal conversion stage. USE - For TTL, ECL or CMOS logic conversions.
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申请公布号 |
DE4127212(A1) |
申请公布日期 |
1993.02.18 |
申请号 |
DE19914127212 |
申请日期 |
1991.08.16 |
申请人 |
LICENTIA PATENT-VERWALTUNGS-GMBH, 6000 FRANKFURT, DE |
发明人 |
KLING, HELMUT, DR.RER.NAT., 7915 ELCHINGEN, DE |
分类号 |
H03K19/0185 |
主分类号 |
H03K19/0185 |
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