Storage capacitor enveloping bit-line of DRAM device - allows straight-line layout of bit-line(s) and increases capacitor area resulting in easier mfr. and better margins

摘要

The storage cel of a semiconductor device, which fundamentally consists of an access transistor and storage capacitor connected to a bitline and workline, features a storage capacitor electrode (37) shaped as a tube in which the bitline metallisation is contained. The source, gate and drain of the storage cell are arranged in-line with the tube. The active part of the capacitor is arranged parallel to or over th bit-line. Two mfg. process flows are also claimed. USE/ADVANTAGE - Allows straight bitlines to be made, in which the storage capacitor contacts and the bitline contacts are directly in-line. This reduces problems during the phot resist stages of the process and allows the capacitance to be enlarged without increasing the cell area. The process is used in the mfr. of DRAMs.